`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/09/15 23:52:14
// Design Name: 
// Module Name: LD
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////
`include "opcode.v"


module LD(
    input   wire [31:0] i_inst,
    input   wire [4:0]  i_rs,
    input   wire [4:0]  i_rt,
    
    output  wire        o_delay,
    output  wire        o_ndelay
    );
    
    wire [4:0] dst;
    wire [5:0] op;
    assign dst = i_inst[20:16];
    assign op = i_inst[31:26];
    
    wire is_load;
    assign is_load = op == `OP_LW;
    
    wire delay;
    assign delay = is_load == 1 && (i_rs == dst || i_rt == dst);
//    assign delay = 0;
        
    assign o_delay = delay;
    assign o_ndelay = !delay;
    
endmodule
